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features ? four short-circuit-protected high-side drivers with a maximum current capability of 50 ma each four short-circuit-protected low-side drivers with a maximum current capability of 50 ma each on resistance high side r on < 10 ? versus total temperature range on resistance low side r on < 7 ? versus total temperature range short-circuit detection of each driver stage disabling of driver stages in the case of short-circuit and overtemperature detection independent control of each driver stage via an 8-bit shift register status output reports short-circuit condition status output reports when all loads are switched off timing of status output reset signaliz es failure mode temperature protection in conjunction with short-circuit detection 1. description the u6820bm is a driver interface in bcdmos technology with 8 independent driver stages having a maximum current capability of 50 ma each. its partitioning into 4 high-side and 4 low-side driver stages allows an easy connection of either 4 half- bridges or 2 h-bridges on the pc board. the u6820bm communicates with a micro- controller via an 8-bit serial interface. in tegrated protection against short circuit and overtemperature give added value. emi prot ection and 2-kv esd protection together with automotive qualification referring to conducted interference (iso/tr 7637/1) make this ic ideal for both automotive and industrial applications. figure 1-1. block diagram v cc status clk di cs hs4 hs3 hs2 hs1 thermal protection 6 9 8 1 control logic 16 3 power-on reset v cc v cc 2 7 10 15 5 v cc v cc 4 14 11 13 12 ls1 ls2 ls3 ls4 gnd cc h h 3 s s 4 s 2 s 1 l s 3 l s 4 l s 2 l s 1 input register h h current limiter current limiter current limiter current limiter current limiter current limiter current limiter current limiter gnd s v s dual quad bcdmos driver ic u6820bm rev. 4527b?bcd?09/05
2 4527b?bcd?09/05 u6820bm 2. pin configuration figure 2-1. pinning so16 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 vs gndcc gnds vcc ls2 hs2 hs1 ls1 status di clk cs ls3 hs3 hs4 ls4 table 2-1. pin description pin symbol function 1 hs1 output high side 1 2ls1output low side 1 3 vs supply voltage 6v to 18v 4 gndcc digital ground 5 gnds power ground 6 vcc supply voltage 5v (external) 7ls2output low side 2 8 hs2 output high side 2 9 hs3 output high side 3 10 ls3 output low side 3 11 cs set supply status (chip select) 12 clk clock line for 8-bit control shift register 13 di data line for 8-bit control shift register 14 status status output (h = fault, diagnostic ?h? if all driver stages are switched off) 15 ls4 output low side 4 16 hs4 output high side 4
3 4527b?bcd?09/05 u6820bm 3. description of the control in terface to the microcontroller the serial-parallel interface basically includes an 8-bit shift register (sr), an 8-bit command reg- ister (cr) and a 4-bit counter. the data input takes place with commands at pins di (data input), cs (chip select) and clk (clock). with a falling edge at clk, the information at di is transferred into the sr. the first infor- mation written into the sr is the least signi ficant bit (lsb). the pin status is used for diagnostic purposes and reports any fault condition to the microcontroller. the input cs in accordance with the cr controls the serial interface. a high level at cs disables the sr. with a falling edge at cs, the sr is enable d. the cr control allows only the first 8 bits to be transferred into the sr, and further clocks at cl k are ineffective. if a rising edge occurs at cs after 8 clocks precisely, the information from the sr is transferred into the cr. if the number of clock cycles during the low phase of cs was less or more than eight transitions, no transfer will take place. a new command switches th e output stages on or off immediately. each output stage is controlled by one specific bit of the cr. low level means ?supply off? or inactive, and high level means ?supply on? or acti ve. if all 8 bits are at a low level, the output stages will be set into standby mode. if one of the output stages detects a short circuit and additionally overtemperature condition, the corresponding control bit in the cr is set to low. this reset has priority over an external com- mand to cr, thus, this does not affect the 1 st control bit. the priority protects the ic against overtemperature by activating the temperature shut down immediately. 4. the status output the status output is at low level during normal operation. if one or more output stages detect short circuit or if overtemperature is indicated, the status output changes to high level (or-connection). for diagnostic purposes (self test of the status output), the status output can also be brought into high level during standby mode. 4.1 timing of the status output reset signalizes the failure mode the use of different reset conditions at the status output simplifies the failure analysis during normal operation, and is also beneficial during testing. the storage content can be used for status output . it is indicated and latched immediately with the rising edge of cs at status output if less than 8 clocks were received during the low phase of cs. the reset is initiated by the falling edge of the 8 th clock (bit 7) of the next data input. also, the appearance of more than 8 clocks is latched and indicated at status by the rising edge of the 9 th clock. the reset is initiated by the falling edge of the 2 nd clock (bit 1) of the next data input. the detection of overtemperature is latched internally. it is reset by the falling edge of the 4 th clock (bit 3) of a data transfer if overtemperature is no longer present.
4 4527b?bcd?09/05 u6820bm 4.2 power-on reset after switching on the supply voltage, all data latches are reset and the outputs are switched off. the typical power-on reset threshold is v cc = 3.7v. the outputs are activated after the first data transfer. 4.3 short-circuit protection the current of the output stages is limited by an active feedback control. short circuit at one out- put stage sets the diagnostic pin 14 (status) to high. in case of both conditions, short circuit at one of the outputs and temperature detection, the affected output is switched off selectively. it will be activated again after the first new data transfer. 4.4 inductance protection clamping diodes and fets are integrated to protect the ic against too high or too low voltages at the outputs. they prevent the ic from latc h up and parasitic currents which may exceed power dissipation. 4.5 temperature protection the ic is protected by an overtemperature detec tion. as soon as t he junction temperature t j = 155c typically is exceeded, the diagnostic pi n 14 (status) is set ?high?. general overtem- perature detection along with short-circuit condition at a specific output result in temperature shut down at that specific output. after temperature shut down, the data input register has to be set again with a hysteresis of typically ? t = 15k (t j = 140c). 4.6 esd protection all output stages are protected against electrosta tic discharge up to 5 kv (hbm) with external components (see figure 8-1 ), all other pins are protected up to 2 kv (hbm). table 4-1. timing of the status output shift register command register condition low-side switch high-side switch status ls1 ls2 ls3 ls4 hs1 hs2 hs3 hs4 set reset 0000000000000000 all out = ok off off off off off off off off h new cs 1111111111111111 all on = ok on on on on on on on on l 0000000100000001 e.g. one on = ok off off off off off off off on l 0111111101111111 short at ls3 off on on on on on on on h no short 1111111111101111 temp & short at hs4 on on on off on on on on h new cs4 1100001100000000 v vcc < 3.7 v = p-on off off off off off off off off h p-on, cs 11100011 xxxxxxxx cs with less 8 clk x x x x x x x x h new cs 8 00011100 xxxxxxxx cs with more 8 clk x x x x x x x x h new cs 2
5 4527b?bcd?09/05 u6820bm figure 4-1. data transfer timing diagram table 4-2. ac characteristics for testing specification conditions minimum maximum unit t r (rise) 10% to 90% v cc on clk, di and cs 10 ns t f (fall) 10% to 90% v cc on clk, di and cs 10 ns t clkp 1/2 v cc 250 ns t clkh 1/2 v cc 100 ns t clkl 1/2 v cc 100 ns t clkcs 1/2 v cc 150 ns t csclk 1/2 v cc 100 ns t diclk 1/2 v cc 80 ns t dih/l 1/2 v cc 100 ns t clkcsh 1/2 v cc 100 ns t cs 1/2 v cc 250 ns t csclk t clkp t clkh t clkl t diclk t dih/l t clkcs 50% 50% 50% t clkcsh t cs clk di cs 90 % 10% t r 90 % t f lsb msb
6 4527b?bcd?09/05 u6820bm figure 4-2. block diagram of the control interface cl din en q7 h4 q6 h3 q5 h2 q4 h1 q3 l4 q2 l3 q1 l2 q0 l1 shift register sr p-on-reset th-protection di cs clk r cl nq d dff q cl r nq d dff q l s 1 _ o n i s c _ l s 1 i s c _ l s 2 i s c _ l s 3 i s c _ l s 4 i s c _ h s 1 i s c _ h s 2 i s c _ h s 4 l s 2 _ o n l s 3 _ o n l s 4 _ o n h s 1 _ o n h s 2 _ o n h s 3 _ o n h s 4 _ o n i s c _ h s 3 status s t d _ b y r cl nq d q dff serial-parallel interface clk 12 13 11 14 r cl nq d dff q norm = 0 n o r m = 0 load cr lsb h if 8 h if 4 h if 2 all norm = 0 cl r d q dff nq por norm=0 8clk q1 2 q2 4 q3 8 cl r en q0 1 counter nr nq cl din nr nq din nr nq din nr nq din nr nq din nr nq din nr nq din nr nq din command register br
7 4527b?bcd?09/05 u6820bm 5. absolute maximum ratings stresses beyond those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions beyond t hose indicated in the operational sections of this specification is not implied. exposure to absolute maximum rati ng conditions for extended periods may affect device reliability . parameters pin symbol minimum maximum unit supply voltage 3 v vs ?0.3 +40 v logic supply voltage 6 v vcc ?0.3 +7 v logic input voltage 11, 12 13 cs, clk, di ?0.3 v vcc + 0.5 v logic output voltage 14 status ?0.3 v vcc + 0.3 v input current 3i vs 0.2 ma 6i vcc 5ma output current (internally limited) 1-2, 8-11, 15-16 i 1h-4h and i 1l-4l 30 65 ma junction temperature range t j ?40 +150 c storage temperature range t stg ?55 +150 c 6. thermal resistance parameters symbol value unit junction ambient r thja 110 k/w junction case r thjc 26 k/w 7. operating range parameters pin symbol value unit supply voltage 3 v vs 6 to 18 v logic supply voltage 6 v vcc 4.5 to 5.5 v logic input voltage low 11, 12, 13 cs, clk, di ?0.2 to (0.2 v vcc )v logic input voltage high 11, 12, 13 cs, clk, di (0.7 v vcc ) to (v vcc + 0.3) v logic output voltage (1 ma load) 14 status 0.5 to (v vcc ? 1) v clock frequency f clk 5mhz junction temperature range t j ?40 to +150 c
8 4527b?bcd?09/05 u6820bm 8. electrical characteristics 7v < v vs < 40v; 4.5v < v vcc > 5.5v; ?40c < t j < 150c; unless otherwise specified no. parameters test conditions pin symbol min. typ. max. unit type * 1 current consumption 1.1 supply current vs no external load 3 i vs 0.2 ma a 1.2 supply current vcc no external load 6 i vcc 5maa 1.3 power-on reset threshold 6 v cc por 3.43.74.0v a 1.4 power-on reset delay time after switching on v cc 6t d por 60 95 130 s d 2 thermal shutdown 2.1 thermal shutdown set t j pw set 140 155 165 c a 2.2 thermal shutdown reset t j pw reset 130 135 155 c a 2.3 thermal hysteresis dt 20 k a 3 output specifications (1l - 4l, 1h - 4h) 3.1 on-resistance low i out = 26 ma, t j = 125c 2, 7, 10, 15 r dsonlow 347 ? a 3.2 on-resistance high i out = 26 ma, t j = 125c 1, 8, 9, 16 r dsonhigh 46.2510 ? a 3.3 output leakage current lowside v lside 1-4 = 17.5v 2, 7, 10, 15 i lowside 5aa 3.4 output leakage current highside v hside 1-4 = 0.5v 1, 8, 9, 16 i highside ?5 a a 3.5 output leakage steepness 1-2, 7-10, 15-16 dv out/ dt 50 200 400 mv/s d 3.6 over current limitation highside 1, 8, 9, 16 i highside 27 45 95 ma a 3.7 over current limitation lowside 2, 7, 10, 15 i lowside 27 45 80 ma a 4 serial interface ? inputs: cs, clk and data 4.1 input voltage low level threshold 11-13 v ilow 0.2 v vcc va 4.2 input voltage high level threshold 11-13 v ihigh 0.7 v vcc va 4.3 hysteresis of input voltage 11-13 ? v i 300 mv a 4.4 pull-down current (internal pull-up resistor: 30 k ? to 140 k ? ) 11-13 i i 300 a a 5 serial interface ? output: status 5.1 output voltage low level i = 1 ma v olow 0.5 v a 5.2 output voltage high level i = 1 ma v ohigh v vcc ? 1 v vcc va *) type means: a =100% tested, b = 100% correlation tested, c = characterized on samples, d = design parameter
9 4527b?bcd?09/05 u6820bm figure 8-1. application circuit note: it is strongly recommended to connect the blocking capacitors at v s and v cc as close as possible to the power supply and gnd pins. recommended value for v s is less than 100 f electrolytic in parallel with 100 nf ceramic. value for electrolytic capacitor depends on external loads, noise and surge immunity efforts. recommended value for v cc is 33 f electrolytic in parallel with 100 nf ceramic. the 4- ? resistors connected to the pins hs1 - hs4 support the protection in case of a short circuit of these pins to v batt . ls2 ls3 ls4 status r * r * r * r * r * = ca. 4 ohm (i lim for inv. supply) c 4.7nf typical application with 4 hall-ics for rotational speed detection 27k 27k 27k 4.7nf 4.7nf 4.7nf 4.7nf 100 4.7nf 100 4.7nf 100 4.7nf 100 33f v batt 100nf v cc 100nf 5 v 12 v 27k sensor control + 47f + v cc clk di cs hs4 hs3 hs2 hs1 thermal protection u6820bm 6 9 8 1 control logic 16 3 power-on reset v cc v cc 2 7 10 15 5 v cc v cc 4 14 11 13 12 ls1 gnd cc h h 3 s s 4 s 2 s 1 l s 3 l s 4 l s 2 l s 1 input register h h current limiter current limiter current limiter current limiter current limiter current limiter current limiter current limiter gnd s v s rr lr rf lf
10 4527b?bcd?09/05 u6820bm 10. package information 11. revision history 9. ordering information extended type number package remarks U6820BM-MFPG3Y so16 taped and reeled, pb-free technical drawings according to din specifications package so16 dimensions in mm 10.0 9.85 8.89 0.4 1.27 1.4 0.25 0.10 5.2 4.8 3.7 3.8 6.15 5.85 0.2 16 9 18 please note that the following page numbers referred to in this section refer to the specific revision mentioned, not to this document. revision no. history 4527b-bcd-09/05 ? put datasheet in a new template ? pb-free logo on page 1 added ? new heading rows on table ?absolute maximum ratings? on page 7 added ? table ?ordering information? on page 10 changed
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